A layout of a carbon nanotube field-effect transistor (CNTFET) is shown in Figure 1. The area of the channel is defined by the width (W) of the source and drain contacts and the length (L) of the nanotube. Details of the ballistic MOSFET modeling can be found in our previous work 3 .

The analytical carbon nanotube model comes from the work of Rahman et al. 4 5 where we have extended the universal DOS spectral function into a numerical calculation for CNT conduction subbands. We have modified the DOS subroutine 6 to account for multimode transport 7 . To improve precision and accuracy in the simulation, the parameters in Table 1 for MOSFET and CNTFET which incorporate quasi-ballistic transport scattering are extracted from CADENCE 8 and Javey et al. 9 , respectively. CNTFET analytical models have been validated and agree well with experimental data 9 10 particularly in the saturation region depicted in Figure 2.

If a CNT can achieve the same current as a MOSFET, an identical channel area (A _MOS = A _CNT) can be maintained by setting the width of the physical space occupied by the CNTFET to be W _CNT = A _MOS / L _CNT. When W = L for the MOSFET, the general channel area can be expressed as A = (kL)², where k is the scaling factor. As such, a CNT channel with length, 2kL should attain the same current with W = 0.5kL. Thus, if the physical width of the CNT channel is W ≤ 0.5kL, there will not be any area drawback in output current due to the longer L. In fact, the maximum electric field in CNT is halved, giving E _mCNT = E _mSi / 2, and is significantly reduced as the CNT channel grows longer. For a CNT with L = 60 nm compared to a Si MOSFET with L = 45 nm, the maximum electric field is E _m = 0.83 E _mSi.

The top view of CNTFET with the source and drain contacts is shown in Figure 1. The filled black rectangle represents the contact enclosure with dimension extracted from a generic 45-nm MOSFET process design kit (PDK) where S = 20 nm, C = 60 nm, and W _C = L _C = 100 nm. Nine capacitances are introduced into the carbon-based macromodel as illustrated in Figure 3. They are the gate oxide capacitance C _ox, quantum capacitance C _Q, source capacitance C _s, drain capacitance C_d, substrate capacitance C _sub, source-to-bulk capacitance C _sb, drain-to-bulk capacitance C _db, gate-to-source capacitance C _gs, and gate-to-drain capacitance C _gd. The size of the contact is crucial as it ultimately influences C _sb and C _db. They are given in Table 1 and can be written as

C sb or C db = ε ins W L t ins ,

where t _ins is the thickness of the insulator, W is the width of the contact, L is the length of the contact, and ε _ins is the permittivity of the insulator. The substrate insulator capacitance C _sub for CNTFET is given by

C sub _ CNTFET = 2 π ε ins ln 4 t sub d ,

where t _sub is the substrate oxide thickness and d is the diameter of CNT. The intrinsic gate capacitance C _G of CNTFET is a series combination of gate oxide capacitance C _ox and quantum capacitance C _Q 11 . The C _ox of a CNTFET 12 13 14 is shown to be

Nanotube C ox = 2 π ε ins ln 2 t ins + d d

The quantum capacitance is expressed by 15 16 17

C Q = 2 g v g s q 2 h v F ∑ i E E 2 − E Gi / 2 2 Θ E − E Gi 2 ,

where g _s is the spin degeneracy, g _v is the valley degeneracy, E _Gi is the bandgap energy, and v _F is the Fermi velocity. The step function Θ x is equal to 1 when x > 0 and 0 when x < 0. The C _gs and C _gd are given as

C gs = L g C ox 2 C Q + C s C tot + C Q ;

C gd = L g 2 C ox C Q + C d C tot + C Q ,

where C _s and C _d are the source and drain capacitance fitting parameters, respectively, 1 2 that are used to fit the experimental data and L _g is the length of the gate. The sum of C _gd and C _db gives the intrinsic capacitance C _int.

The square law is no longer valid for I-V formulation of short-channel MOSFET. Tan et al. 3 succinctly show the transformation of the square law that applies for the long channel to the linear law that is applicable for short-channel MOSFET. On the other hand, I-V formulation for the CNTFET model follows the quantum conductance principle that was developed by Rahman et al. 4 5 and Datta 6 . The I-V model can be rewritten in terms of drain voltage V _d, source voltage V _s, and gate voltage V _G that is expressed by

I ds V G , V d , V s = G ON k B T q log 1 + exp q E F − V sc V G , V d , V s / k B T − G ON k B T q log 1 + exp q E F − V sc V G , V d , V s − V d − V s / k B T ,

where G _ON is the ON-conductance, V _sc is also known as the channel surface potential 11 , E _F is the Fermi energy, k _B is the Boltzmann constant, T is the temperature, and q is the electric charge. The equation is iteratively solved and hence includes the effect of gate voltage.

In this section, the potential of CNT circuit design is assessed. Our simulation results in Figure 4 indicate that CNTFET is able to provide drain current performance comparable to a 45-nm-gate length MOSFET. The model is successful in predicting expected output current levels in a sub-100-nm-channel CNT transistor experimental data. The DIBL effects and subthreshold swing (SS) are better suppressed in the CNT device, while the Si transistor demonstrates a moderate DIBL and SS due to short-channel effects as shown in Table 2. Although the CNT has similar ON-current, it sustains I _on/I _off ratio of two orders of magnitude lower than Si MOSFET. The quantum ON-conductance limit of a ballistic single-walled carbon nanotube (SWCNT) and graphene nanoribbon with perfect contact is G _ON = 4e ²/h and G _ON = 2e ²/h (twice the fundamental quantum unit of conductance), respectively. Quantum capacitance C _Q is directly proportional to the density of states of the semiconductor but inversely proportional to the electrochemical potential energy. When C _Q becomes smaller than C _ox, a large quantity of the electrochemical potential energy is needed to occupy the states above the Fermi energy. This results in the reduction in overall intrinsic gate capacitance C _G and limits the channel charge in a semiconductor and ultimately the I-V characteristic of the FET devices. Comparison in Table 2 shows that MOSFET has a higher cutoff frequency due to higher transconductance as compared to CNTFET with lower capacitances.

First, MOSFET logic circuits are built based on a 45-nm generic PDK. The MOSFET designs are then compared with carbon-based circuit models that consist of prototype digital gates implemented in HSPICE circuit simulator. These CNTFETs use 45-nm process design rules, namely the minimum contact size. For a fair assessment, both MOSFET and CNTFET are designed to provide similar current strength (≈46 to 50 μA).

An appropriate CNTFET device was fabricated to investigate the contact resistance. SWCNTs were grown in situ using the bimetal catalyst iron-molybdenum (Fe-Mo) 11 on a silicon-on-insulator substrate with 200 nm of thermally grown SiO₂. Metal contacts were patterned by electron beam lithography, and 60 nm of palladium (Pd) contacts was deposited to form a back gate geometry transistor. The spacing between the Pd contacts varied between 56.6 nm and 1.06 μm as shown in Figure 5.

A four-probe measurement was carried out at room temperature to extract the resistance characteristics of the carbon nanotube that was used to form the transistor channel. The normalized resistances were 0.495, 0.744, 0.118, and 0.450 MΩ/nm for R _2,3, R _2,4, R _3,4, and R _4,5, respectively, where indices indicate Pd contact labels. The diameter of the SWCNT is 1.5 nm. Calculation shows that the 415-nm nanotube resistance is 27.8 kΩ that is almost equal to the theoretical R _ON = h/q ² = 25.812 kΩ and four times larger than the theoretically lowest quantum resistance of the SWCNT, R _ON = h/4q ² = 6.5 kΩ.

Though at 415-nm channel length ballistic transport is not preserved in the CNT, it is still only factor 4 larger than the theoretically expected minimum, suggesting that scattering is not extensive. Nevertheless, the model which assumes ballistic transport predicts similar saturation current levels (≈50 μA) for both the 50- and 415-nm channel devices, as illustrated in Figure 5. Practically, this suggests that one must have CNT channel lengths below approximately 100 nm or even low contact resistance in order to utilize ballistic transport in them.

CNT circuit logic operation is simulated in HSPICE based on the compact models described in the ‘Model verification’ section. Figures  6, 7, 8, 9, and 10 show the schematic of NOT, NAND2, NOR2, NAND3, and NOR3 gates and their corresponding input and output waveform, respectively. It is shown that CNTFETs are able to provide correct logical operation as MOSFET from the output waveform. In this simulation, it is assumed that both the n-type and p-type CNTFETs have symmetrical I-V characteristics. The performance evaluation of these Boolean operations is listed in Table 3.

The unity current gain cutoff frequency for the CNTFET circuit model is depicted in Figure 11. The model uses a copper interconnect of 45 nm with a 100-nm and 500-nm substrate insulator thickness. The interconnect length varies from 0.01 to 100 μm. The length of interconnects affects considerably the frequency response. The lower length interconnect enhances the cutoff frequency. The substrate thickness also plays an active role in lower length domain. No distinction with the substrate thickness is visible beyond 1-μm interconnect length. The figure of merit for logic devices, namely power-delay product (PDP) and energy-delay product (EDP) metrics, are given as

PDP = P av × t p ;

EDP = PDP × t p ,

where P _av is the average power and t _p is the propagation delay.

Figure 12 shows the PDP of CNTFET and MOSFET logic gates for the 45-nm process. The simulation results show that the PDP of CNTFET-based gates are lower than that of MOSFET-based gates by several orders of magnitude 18 . For the 45-nm process, the PDP of CNTFET-based gates is two times smaller than that of MOSFET-based gates with L _wire = 5 μm. It increases to 1,000 times without interconnect (L _wire = 0 μm).

Figure 13 shows the EDP of CNTFET and MOSFET logic gates for the 45-nm process. EDP for CNTFET-based gates with 5 μm is comparable to MOSFET. As a result, the wire length should be kept shorter than 5 μm in order to obtain energy-efficient low-power architecture.

Figures  14 and 15 show 3D plots of PDP and EDP for CNTFET with copper interconnect up to 5 μm in length. We observe a 28% improvement of PDP while EDP reduces by 39% for NAND3 that adopts the 45-nm process compared to the one that uses the 90-nm process contact size.

Table 3 shows the average propagation delay, t _p, for logic gates NOT, NAND2, NAND3, NOR2, and NOR3 for CNTFET with and without interconnect in comparison with MOSFET during post-layout simulation. It is found that NAND3 or NOR3 has the largest propagation delay since both of them has multiple fan-in and fan-out each. In the digital logic simulation of CNTFET, we use an average length of 5 μm per fan-out.