In general, ferroelectrics are dielectric crystals with the perovskite structure, 22 whose formula is ABO₃ with the schematic structure shown in Figure 1a. The spontaneous polarization arises as the temperature sweeps due to a lattice distortion which involves the relative displacements of B⁴⁺ in each cell. These ferroelectric behaviors appear only under an inherent temperature (Curie temperature T _C). As shown in Figure 1b, the similar polarization phenomenon can also be exhibited from the ferroelectric under the condition of an external electric field (E), in which the intensity of polarization (P) does not exhibit a linear response to E but instead shows a closed hysteretic loop. When E strides a particular value, the polarization is reversed, and we call this value coercive field E _c (see Figure 1b). In other words, P can be switched by modulating E, and the remnant polarization + P _r and − P _r states are stored in ferroelectric. The bistable state of ferroelectric can be programmed as binary information ‘1’ and ‘0’ for NVMDs. Considerable efforts therefore have been taken to exploit available NVMD devices based on this.

A reasonable model is critical in order to take the advantages of ferroelectric for fabricating the NVMDs 52 . The typical memory devices are built on the base of the capacitor 5 53 54 or FeFET 55 56 . The former model consists of a thin ferroelectric film between two conductive electrodes, and the latter one is similar to a metal-oxide-semiconductor field-effect transistor (MOSFET). Figure 2 shows the schematic diagrams of both. Shiga et al. have demonstrated that the signal significantly deteriorates as the capacitor size scales down, which limits the memory capacity to 128 Mb. 57 . The leakage current is another key challenge for the development of capacitor-based NVMDs 58 . On the other hand, FeFET has a well-defined memory switch behavior with simple nondestructive readout (NDRO) process carried out by detecting I _DS or the resistance of the active channel. Due to the excellent performance obtained, the integration of ferroelectrics with nanomaterials has been extensively explored in previous works 2 43 59 60 61 , where ultimate scalability has been reported as well. Thus, in this paper, we give the special attention to FeFET-based memory devices with nanostructures.

Unlike MOSFET, the oxide-gate dielectric is replaced by ferroelectric in FeFET. By modulating the gate bias, the carriers accumulate or deplete at the ferroelectric (FE)-semiconductor interface, leading the FeFET on or off, as shown in Figure 3a,b (a p-channel FeFET) 62 . The corresponding transfer curve of I _DS versus V _G has been depicted in Figure 3c. With the polarization of the FE layer, the curve of I _DS varies with V _G as a hysteretic loop when V _G sweeps upward (from negative to positive) and then downward (from positive to negative) continuously. Moreover, even if V _G is released, the charges remain; thus, the device retains its state. Therefore, as V _G = 0 V, the device still exhibits an on or off state, which can be defined as 1 and 0. In other words, the information in FeFET is not lost even when encountering a power outage. The information can be read out by detecting the I _DS or the resistance of the active channel. Figure 3c is the corresponding closed hysteretic loop of I _DS versus V _G, which shows the track of switching between the 0 and 1 state. It's evident that the appropriate large value of P _r and low E _C are important for the performance of FeFET 59 63 . A too low P _r may not be able to induce enough accumulated carriers at the FE-semiconductor interface to give rise to an evident change of conductance of the channel. On the other hand, although a low E _C can realize a low operating bias, it also raises a serious accompanying instability problem since a low voltage is not enough to switch the states of the device, which can be solved by the concessive method using a thick FE layer. In general, the properties of ferroelectric are essential for the fabrication of FeFET.

Based on the traditional thin-film FET, it is easy to fabricate a thin-film FeFET. Although its simple structure can supply easy fabrication 64 , it also suffers from several problems which need to be solved 65 66 . For example, the E _C of the film is typically several kilovolts per centimeter, which requires a high operating voltage to reverse the polarization. Moreover, the poor polarization value can hardly effect an evident conductance change 67 . On top of these, the low field-effect mobility, low on/off ratio, low subthreshold slope, and the poor switch speed are limitations impacting the applications of the thin-film FeFET 68 69 70 . In recent years, oxide NWs have emerged as promising building blocks in various technological domains including fundamental researches and nanodevice applications due to their unique structures and stable properties 71 72 . Tremendous efforts have been made to fabricate NW FeFETs, which use the NWs as the active channel. In the early days, In₂O₃ NWs have been integrated with lead zirconate titanate (PZT) to fabricate FeFET. Due to the high dielectric constant and the switchable spontaneous polarization of PZT, the fabricated device received an enhanced performance and memory effect 25 , when compared with the traditional SiO₂-gate FET. The schematic diagram is shown in Figure 4a, which reveals that the back-gate FeFET structure has been used in this research. The In₂O₃ NWs with a diameter of 10 nm were first ultrasonicated in isopropanol and then deposited onto the PZT/Pt/SiO₂/Si substrate by spin-coating technique. Photolithography, Ti/Au deposition, and lift off were carried out subsequently to pattern the source and drain electrodes, which were in contact with an individual NW. The fabricated FeFET operated on an accumulation/depletion mode with the conduction of the active NW channel modulated by the gate potential. Figure 4b shows the transfer curves of the memory device, exhibiting a closed counterclockwise loop, when V _G was sweeping upward and then downward. As V _G = 0 V, there were two pronouncedly different values of I _DS, which were caused by the switchable P _r of the PZT layer. Hence, we could define the larger one as a binary 1 and the smaller one as 0 to realize the basic program function. Moreover, the methods used in this experiment could be generalized and applied to other NW systems to obtain nanoscale memory devices.

Having inherent defects in ZnO NWs, such as oxygen vacancies and Zn interstitials, ZnO NWs present the character of the natural n-type semiconductor 73 . In Liao's recent work 2 , ZnO NW was combined with PZT thin film to realize the memory function successfully. The schematic diagram and scanning electron microscopy (SEM) image were shown in Figure 5a,b, respectively. As ZnO NW is an n-type semiconductor, with the polarization of PZT, a positive pulse gate voltage would raise up the band of the channel and then deplete the electrons in the NW, as shown in Figure 5c. The device presented an effectively ‘off’ state, which could be defined as a binary 0. The binary 1 representing the opposite state could be defined as well in Figure 5d. Based on this principle, the state of the device could be switched by a timely pulse; in other words, the programming process was realized. The transfer character also demonstrated the switching mechanism with two pronounced states at V _G = 0 V, which is shown in Figure 6a. Reading cycles of 10³ of both 1 and 0 states were carried out in Figure 6b. As we can see, the two states were still well distinguishable, showing a sustaining memory performance.

Despite the achievements made with the NWs, which yield many attractive features and desirable capability for potential applications, there are still many more new approaches coming up to further improve the integrated density. The multi-bit FeFET has been considered to supply higher density for storage, which could overcome the scaling limitations and economic challenges in the current silicon industry. The ZnO NW FET (Figure 7a) with coated ferroelectric BaTiO₃ (BTO) NPs has realized the function for a two-bit memory 17 . Figure 7b,c showed the schematic view of the differing degrees of reoriented electric dipole moments when a positive and negative bias was applied, respectively. The polarization of the NPs gave rise to a higher positive gate bias and then induced more polarized NPs. The more polarized charges were accumulated at the NP-NW interface, the larger the conductance of the active channel was. The surface engineering further caused a positive shift of the threshold voltage (V _th). In Figure 8a, it's obvious to find that V _th was dependent on the sweep range of the gate voltage as well as the sweep direction. A more negative initial sweep voltage caused a more positive shift of V _th. Similarly, a more negative threshold voltage shift was related to a more positive initial sweep voltage. In addition, as mentioned previously, the information could be read out by detecting the current or the active channel resistance, so an individual device used herein could store multi-bit information with different gate voltage pulses. The different states of the I _DS were corresponding to different binary information, which could be modulated by varying gate voltage pulses. Figure 8b showed the detailed practical process of programming ‘00’, ‘01’, ‘10’, and ‘11’ states. With the ability of storing multi-bit information in an individual memory device, the device reported herein provided a new way to enhance the integrated density.

Furthermore, the synthesis methods applied here demonstrated a simple room-temperature process for integrating the FE NPs with ZnO NW to fabricate the multi-bit memory device. The device fabricated in this way had a remarkably high on/off ratio of 10⁴ and a long retention time over 4 × 10⁴ s, which made it easy to recognize the two binary states. This work thus provided a viable route to fabricate high density NVMDs to overcome the existing physical and technological limitations.

In order to exploit the bottom-up technology, extensive studies on 3D structure-based devices have flourished, inspired by the peculiar prosperity of the architectures. Depending on the kinetics of the growth process, two crystal structures of one same compound can exist stably. Despite the changes in size, the additional structure provides more electronic states and characters. These special features provide the precious opportunity for making efficient nanodevices. CdS nanotetrapods provide a typical example in which each individual nanotetrapod is combined with the pyramidal-shaped zincblende structure core and wurtzite arms, with the electrons and holes located in each other, respectively. Moreover, the bandgap of the arms is larger than the one of the core. With the type II band alignment, a peculiar electron transport is observed.

Due to the unique and also discommodious 3D structure, CdS nanotetrapods were impossible to lie flat on the gate, resulting in poor capacitance coupling, whereas the ferroelectric with high dielectric constant can make up it; therefore, the memory effect was also observed 35 . Figure 9a shows the schematic diagram, Figure 9b,c shows the transmission electron microscopy (TEM) images of CdS nanotetrapods, and Figure 9d,e shows the SEM images of the device. To investigate the performance of the prepared device, the transfer character of the device was measured with the gate voltage swept upward and then downward continually under various temperatures (see Table 1). It is obvious that a counterclockwise hysteretic loop is presented at 300 K, whereas a clockwise hysteretic loop is presented at 80 K. The phenomenon in Figure 1a could be attributed to the ‘charge-store’ memory effect 74 . The defects in the FE layer and the FE-CdS interface provided the low potential site for storing charges which affects the distribution of the charges in the active channel, just like floating gates. On the other hand, the typical ferroelectric memory clockwise loop in Figure 10b indicated that the ferroelectric memory played the dominant role at low temperature. The charge-store memory effect competed with ferroelectric memory as the temperature varied. This was demonstrated by the curve at 140K where no evident hysteretic loop was present (Figure 10c). At low temperature, few trapped charges were active, and the charge-store effect became frozen 75 ; therefore, the ferroelectric memory effect became dominant, which was proved by the ferroelectric character at 8.5K (Figure 10d). The positive voltage led to − P _r in the FE layer and an upward band of core, resulting in a higher potential barrier on the core/shell interface which gave rise to a lower conductance and a positive shift of the electric spectra, as shown in Figure 10d. The binary 1 and 0 can then be defined at 8.5 K, respectively.

The performance of the oxide NW-based FeFET is predetermined by the material properties, such as the intrinsic defects and poor field-effect mobility. As a flexible and high carrier mobility material with no dangling bond, the carriers in the carbon nanotube (CNT) can realize 1D near-ballistic transport at room temperature 76 77 , which is the inherent property that is absent in the traditional oxide NWs 36 . Due to the decrease of the density of states over the increasing energy, the same amount of carriers can induce a more intensified shift of Fermi level than in traditional oxide NWs 37 . CNT therefore has attracted more and more attention with new researches focusing on fabricating CNT-based FET in the past decades 78 79 . With the narrow bandgap of 0.5 eV, the depolarization field is suppressed in CNT, which supplies a much more stable remnant polarization than the traditional oxide NWs. Thus, the enhancement of performance can be obtained from the CNT-based FeFET memory device. However, there still exist many intrinsic flaws in the fabrication of FeFETs. For example, the defects on the interface between the FE layer and single-wall carbon nanotube (SWCNT) can trap charges and hence lead to deterioration of polarization. In addition, the temperature-dependent charge-store memory effect is not controllable as the amount and the distribution of the defects are uncontrollable 80 . Hence, controlling the ‘floating gates’ distributed along the SWCNT channel has been proved difficult.

Based on an excellent FE-CNT interface with few defects in the FE layer, an intrinsic ferroelectric memory FeFET was fabricated by integrating BTO with SWCNT 38 . The moderate preparation process has been carried out to reduce the interface reaction: BTO was pre-prepared on a smooth Nb-doped (001) SrTiO₃ (STON) substrate by pulsed laser deposition (PLD). Then, the temperate method of spin coating was utilized to deposit SWCNTs onto BTO. Figure 11a showed the schematic diagram of the memory device. The TEM image of the microstructure of the memory device was also displayed in Figure 11b, which revealed a coherent epitaxial growth of BTO on STON. The typical clockwise hysteresis loop was shown in Figure 11c. As we mentioned previously, the V _th shift was in accordance with the variation of the sweeping region and the initial value. The V _th values of the device herein were 2.5 V and −1.5 V as V _G swept upward and downward, respectively, which supplied a wide memory window of 4 V. Thus, when a positive pulse was applied on the active SWCNT channel (assuming a positive voltage of drain-source), the polarization of BTO went from the FE layer towards the SWCNT. When the pulse was released, a high barrier was induced by the downward band bending of SWCNT. Hence, the device was effectively at off state, which could be defined as binary 0. The binary 1 could be defined correspondingly as well. A series of homologous pulses tracking the hysteresis loop could therefore realize a sequence of erases and writes. It should be noted that a compromised hysteresis loop has been observed when the gate voltage was below 1 V, as shown in Figure 12a, whereas the coercive voltage of the FE layer herein was about 2 V. To further investigate this interesting behavior, a theoretical simulation was performed. As shown in Figure 12b,c, the electric field at the interface between the SWCNT and FE layer was far more than E _C caused by the ultrathin SWCNT; thus, the device could still remain valid at the gate voltage of less than 1 V. Therefore, CNT FeFET offers great potential for manufacturing low-power consumption NVMDs. For a coherent study of this work, a double-gate SWCNT FeFET (a two-bit memory device) was fabricated with the similar technology roadmaps. The schematic maps of the fabrication are shown in Figure 13a,b,c 38 . As a p-type intrinsic SWCNT FeFET memory device, with V _DS = 10 mV, the device was turned off when a positive gate pulse (2 V) was applied on both gates, which corresponded to the program process of erasing the information stored to binary state 00. The binary information of 01 could be written into an individual FeFET by applying a low bias of −0.5 V on gate 2, which was lower than the threshold voltage yet not enough to induce an efficient polarization in the FE layer. As a result, gate 1 became off (binary 0 state) and gate 2 became on (binary 1 state). The whole program process is shown in Figure 13e, which exhibits a high mobility of approximately 10³ cm² V⁻¹ s⁻¹ and an ultrahigh integration density of over 200 Gbit/in.². This is highly desirable for the practical applications.

Unlike the traditional semiconductor, graphene does not have bandgap. Therefore, the graphene-based FET usually has poor on/off ratio at room temperature 81 82 . Although it has no advantages for digital switches, its high carrier mobility and excellent transconductance make it an ideal material for the radio frequency analog electronics in the logic integrated circuit 83 84 85 86 . The high carrier mobility also makes it a promising candidate for the next-generation ultrafast NVMDs 47 87 . Moreover, the enhanced interfacial coupling makes the performance of the graphene-based memory device much more elevated 43 46 .

The graphene-based FeFET was fabricated using graphene as active channel (Figure 14a) 43 . A 700-nm-thick FE layer of poly(vinylidene fluoride-trifluoroethylene) (PVDF-TrFE) was then spin-coated on the graphene as the top gate. The atomic force microscopy (AFM) image (Figure 14b) showed that the FE layer has formed a continuous thin film. With the switchable polarization of PVDF-TrFE, a resistance hysteretic loop with double peaks was obtained in Figure 15a, due to the induced doping in graphene caused by the flipping electric dipoles. The binary states of 0 and 1 could then be defined as the minimum and the maximum values of R, respectively. With the closed hysteretic loop, the program processes could be realized by sweeping V _G in the specific direction. Regardless of how the binary state transits, the program processes could be realized by following a full loop, as shown in Figure 15c,d,e,f. The graphene-based FeFET featured a high carrier mobility of 200,000 cm² V⁻¹ s⁻¹ and a reading speed as fast as 10 fs. It should be further noted that the pronounced ΔR/R exceeded 200 %, which was essential for the retention time and fatigue resistance. These unique characteristics of graphene-based FeFET offer excellent potential in the applications of ultrafast FeFET-based NVMDs.

According to the model proposed by Dawber 93 and Scott 94 , oxygen vacancies in ferroelectric films are believed to be able to impact the fatigue. Due to the local phase decomposition of ferroelectric and the oxygen vacancy migration towards the FE-electrode interface, accumulating and forming a pin structure, the remnant polarization is dramatically decreased 95 . In the typical example of PZT, the oxide conductive materials were utilized as the electrodes 96 , which effectively blocked the diffusion effect in each interface. The crystalline structures therefore were not corroded, showing no fatigue behavior. The size effect was associated to the fatigue behavior as well. Table 1 shows a few ferroelectric systems and the characteristics of size effect in relation to fatigue behavior 97 .

After a number of switch cycles, the carriers in the semiconductor may inject into the FE layer, which deteriorated the dielectric constant of the FE layer. Moreover, the reduction of remnant polarization was observed after modulating the V _G, as proved by extensive experiments 98 99 100 . Therefore, a high κ buffer was introduced between the FE layer and semiconductor. On one hand, the buffer acted as the diffusion barrier to prevent the ferroelectric from being deteriorated 101 . On the other hand, though the superposed layers were equivalent to two serial capacitors, it made the voltage at the FE layer only slightly smaller than the initial gate voltage 53 . The representative work has been carried out in the early days, which inserted a 13-nm-thick buffer insulation layer of (HfO₂)_0.75(Al₂O₃)_0.25 between p-type Si and a 400-nm-thick FE layer of SBT 14 . Figure 17a shows the schematic structure of the device. As shown in Figure 17b,c, it retained an on/off ratio of more than 10⁶ even after 12 days and endured 10¹² cycles with no changes. Due to the superior retention and endurance, considerable researches have been done to exploit this for practical applications.

The scientific experiments have demonstrated that the interface quality of the device is essential for the fatigue behavior 102 103 . The reduced interaction is beneficial for the fatigue resistance, which was demonstrated by the researches executing a post annealing to obtain enhanced performance 19 . Many new technologies and new materials were also introduced to enhance the fatigue resistance, such as the position controllable dip-pen nanolithography (DPN) technology 104 . In this work, PVDF-TrFE was used as the ferroelectric gate. Unlike the inorganic ferroelectric, organic ferroelectric (PVDF-TrFE) has temperate chemical affinity and lower interfacial tension towards the CNT channel, which led to fewer defects in the interface. Figure 18a,b shows the visualized schematic technology maps of the fabricating process, and Figure 18c was the AFM image of the CNT-based nonvolatile memory device. The introduction of nanodot ferroelectric gate (approximately 9.2 nm) realized a high integration density of the memory device, with the bistable state remarkably well retained at up to 10⁶ s. Moreover, as shown in Figure 18d,e, even after approximately 10¹⁰ switching cycles, the two states were still distinguishable, demonstrating great performance.