Introduction
Due to electron scattering on copper wire surface and grain boundary, the resistivity of a copper wire will increase rapidly when the interconnect feature size becomes smaller than 45 nm
1
. As a result, the time delay of the transmission signal will increase dramatically, which will restrict the circuit performance. Besides, as the integration density of interconnects increases, crosstalk issues will be the concerns. The crosstalk issue directly affects the circuit performance. To address the issues, carbon nanotube (CNT) interconnects have recently been proposed as ideal substitutes in future interconnect designs
2
. CNT can be metallic or semiconducting
3
, depending on their chiralities, and metallic CNTs are the preferred candidates for interconnect applications
4
5
6
.
Although a few studies on the crosstalk noise of CNT-based interconnections have been reported
7
8
, the influencing factors are not fully understood. Crosstalk is the unexpected voltage noise interference due to the electromagnetic coupling of adjacent transmission lines when the signal propagates in the transmission lines. It is well known that crosstalk between interconnects may cause signal delay and glitch that may be propagated to the output of a receiver, which can cause a logic error at the output of the receiving device
9
. Therefore, to understand the influencing factors which affect the crosstalk voltage of single-walled carbon nanotube (SWCNT) interconnects and how to decrease them are particularly important.
In this paper, the main factors affecting the crosstalk of SWCNT bundle interconnects were studied, including the influence of the SWCNTs position when their length is fixed, which was proposed for the first time. Firstly, we considered three coupled SWCNT interconnects to form a standard parallel wire architecture over a ground plane by calculating the coupling capacitances between adjacent interconnects; this model was then extended to the SWCNT bundle by calculating the corresponding parameters.
Methodology
RLC equivalent circuit parameters of SWCNT
The equivalent circuit model based on RLC distributed parameters for an individual SWCNT placed away from a ground plane is shown in Figure 1, and its components are explained in detail
10
11
as follows.
<p>Figure 1</p>Equivalent circuit of an individual SWCNT interconnect
Equivalent circuit of an individual SWCNT interconnect.
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The resistance of a SWCNT contains imperfect contact resistance (R
C) which is in the range of 0 to 120 KΩ, quantum resistance (R
Q) (R
Q = h/4e
2, and scattering resistance (R
S) per unit length (R
S = h/(4e
2·λ
CNT)), where h is Planck's constant, e is the charge of an electron, and λ
CNT is the mean free path length.
The capacitance of a SWCNT includes electrostatic capacitance (C
E) and quantum capacitance (C
Q); the expressions are given by
C
E
=
2
π
ε
/
ln
(
y
/
D
)
and
C
Q
=
2
e
2
/
h
v
F
,
where D is the diameter, y is the distance away from a ground plane treating the CNT as a thin wire, and v
F is the Fermi velocity.
The inductance of a SWCNT includes kinetic inductance (L
K) and magnetic inductance (L
M); the expressions are given by
L
k
=
h
2
e
2
v
F
and
L
M
=
μ
2
π
ln
(
y
D
)
.
For D = 1 nm and y = 1 μm, L
M ≈ 1.5 pH/μm. Clearly, the magnetic inductance can be neglected.
Crosstalk modeling for CNT bundle interconnects
In practice, CNT bundles are closer to actual application than individual CNT. Here, the crosstalk modeling is being established.
Figure 2 shows the cross-sectional view of the interconnect architecture for further characterization of crosstalk effects in SWCNT bundles. The middle signal wire is filled with CNTs, and it is the same as the adjacent interconnects on both sides of the signal. The width and height of the interconnects are W and H, respectively. The spacing between two interlayer interconnects is S, and the thickness of the interlayer-dielectric is T
ox. H = 2W and δ ≈ 0.34 nm, which is the van der Waals gap.
<p>Figure 2</p>Cross-sectional view of the interconnect architecture using SWCNT bundle
Cross-sectional view of the interconnect architecture using SWCNT bundle.
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The total number of SWCNTs (N
CNT) in the bundle is given as
N
CNT
=
N
W
⋅
N
H
-
In
[
N
H
2
]
where
N
W
=
In
[
W
-
D
D
+
δ
]
+
1
and
N
H
=
In
[
H
-
D
(
3
/
2
)
(
D
+
δ
)
]
+
1
,
where N
H is the number of rows in the interconnect bundle, N
W is the number of columns, and N
CNT is the total number of CNTs. Since a SWCNT bundle consists of several individual SWCNT in parallel, the formulas of the resistance, inductance, and capacitance of a SWCNT bundle have been listed in previous papers
12
.
In order to analyze the influencing factors which affect the crosstalk voltage on adjacent wires, we consider the geometry of three parallel SWCNT bundle interconnects as shown in Figure 3. The wire affected by the crosstalk is termed as victim wire, and the wires that cause crosstalk on the victim wire are termed as aggressor wires. The driver and load parameters are also shown here, where R is the equivalent output resistance, and C
L is the input capacitance. To analyze the situation in which there is the largest crosstalk pulse, assume that there is no voltage in the signal line, and the input excitation of the aggressor lines on each side are square wave signal of 1 V with simultaneous switching in the same direction. All geometrical parameters in the simulation below are based on the International Technology Roadmap for Semiconductors (ITRS) 2007
13
.
<p>Figure 3</p>Geometry of three parallel SWCNT bundle interconnect
Geometry of three parallel SWCNT bundle interconnect.
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Results and discussion
The crosstalk voltage in a SWCNT bundle depends on several factors, such as line length, the position when the length is fixed, spacing between SWCNTs, etc., which will be discussed using the RLC model, respectively. Simulations are performed using SPICE simulator.
The crosstalk voltage induced on the victim line by the aggressors for several values of line length for the 14-nm technology node is shown in Figure 4. It can be seen obviously that the peak amplitude and duration increase by increasing the line length. For higher values of length, the crosstalk amplitude keeps a level slightly below 0.15 V, while increase in duration is still applicable. Therefore, for this case, sampling elements with a threshold voltage V
DD/2 = 0.5 V, the induced peak voltage will never reach the threshold voltage, so the induced peak voltage will not produce a logic error at the output of the receiver. Besides, we can reduce the duration time by decreasing the length.
<p>Figure 4</p>The effects of length on the crosstalk noise for the 14-nm technology node
The effects of length on the crosstalk noise for the 14-nm technology node.
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The crosstalk peak voltage of SWCNT bundle interconnects induced on the victim line of different positions for the length fixed as 100 μm is shown in Figure 5. As we can see, with an increase in position, crosstalk peak voltage will increase accordingly. But after the position value reaches about 60 μm, it is almost saturated, which indicates that, if there are adjacent interconnections, it is better to place them at the position where there is small crosstalk when they are designed to reduce the impact of crosstalk. In addition, we can conclude that, with the decrease of technology node, crosstalk peak voltage at the same position of a fixed length will decrease correspondingly. That is to say, with the decreasing of feature size, crosstalk caused by the different positions will be reduced as a whole.
<p>Figure 5</p>The effects of position on the crosstalk noise when length is 100 μm
The effects of position on the crosstalk noise when length is 100 μm.
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The peak voltages induced by the crosstalk versus the spacing are shown in Figure 6. The figure indicates that the induced peak voltages decrease rapidly as the spacing values increase. This is due to the fact that, with an increase in the spacing, the coupling capacitance reduces rapidly. Therefore, the peak voltages due to crosstalk can be significantly reduced by properly setting the spacing between adjacent lines (e.g., from 2 to 8 nm in this case), but beyond this point, noise reductions will saturate. In addition, as feature size becomes smaller and smaller, line spacing cannot be increased infinitely to decrease crosstalk noise, which needs to set spacing properly.
<p>Figure 6</p>The effects of spacing on the crosstalk noise for the 14-nm technology node
The effects of spacing on the crosstalk noise for the 14-nm technology node.
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Figure 7 shows the effects of diameter on the crosstalk noise. The crosstalk peak voltage decreases gradually with the increase of the SWCNT diameter for the technology node of 14 nm. When the feature size is fixed, the larger the diameter, the smaller is the number of SWCNT. The voltage amplitude variation value is about 20 mV when the diameter changes from 1 to 6 nm. We can conclude that crosstalk voltage can be reduced by increasing the diameter.
<p>Figure 7</p>The effects of diameter on the crosstalk noise for the 14-nm technology node
The effects of diameter on the crosstalk noise for the 14-nm technology node.
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Figure 8 shows the crosstalk voltage gain with the frequency change. The main effect is a spread of the curves on the interconnects. It is worthy to note that, despite the length of the interconnects, the crosstalk waveforms show a relative spacing that is almost constant. With increasing the frequency of the aggressor wires, crosstalk voltage first increases and then decreases after it reaches the peak. When the frequency exceeds 1 GHz, crosstalk voltage decreases gradually with the increase of frequency. Therefore, the peak voltage gain due to crosstalk can be significantly reduced by properly setting the frequency.
<p>Figure 8</p>The effects of frequency on the crosstalk noise for the 14-nm technology node
The effects of frequency on the crosstalk noise for the 14-nm technology node.
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