N-type (100)-oriented Si wafers were used as substrates. The backside was implanted by P³¹+ (40 keV, 480 μC), cleaned by plasma and wet cleaning processes and annealed at 900°C for 30 min in N₂ ambient. Before loading the samples into the UHV evaporation chamber, their surface was refreshed in diluted HF. The time elapsed after cleaning to reach 1 Pa pressure in the UHV chamber was about 30 min. After evacuation down to 1 × 10-6 Pa and prior to evaporation, Si wafers were annealed in situ for 5 min at 800°C. Iron has been evaporated from ingots of 99.9% purity using an electron gun at a pressure of 3 × 10-6 Pa by RDE process at 0.015 nm/s rate onto the 600°C substrate, and further annealed for 5 min at the same temperature. Contamination was indicated outside the Fe deposition by SCM 7 . To identify this contamination by DLTS half of the Si wafer fragment was covered during Fe deposition and 400 μm × 400 μm rectangular Au dots Schottky junctions were prepared both in and outside the Fe-deposited area.

SCM was measured by a DI 300 nanoscope equipped with scanning capacitance facility. The capacitance is measured at 1 GHz. The local dC/dV is measured using lock-in technique with bias modulation in the 5-120 kHz range 7 . The heavily doped silicon tip covered by a thin diamond layer, an air gap, and the conductive substrate are evaluated as a simple MOS structure. In this approximation the measured local dC/dV is usually interpreted as dopant concentration under the tip. C-V, I-V, and DLTS characteristics were measured in a SEMILAB 83D system. A preamplifier was developed for the capacitance input of the DLS83D equipment. A 100-nm radius tungsten tip connected directly to the preamplifier input was positioned above the silicon surface. The apparent capacitance was amplified 200 times as it was calibrated by measuring 1 and 5 pF standard capacitances with and without the preamplifier. The amplification of capacitance without increased noise is possible since the low noise preamplifier decouples the load of the measuring cables from the measuring tip. This method will be referred to as scanning tip DLTS.

The spreading resistance (SR) was measured in an SSM130 system using two measuring tips at 100 μm distance. A series of clean silicon with doping in the 0.08-180 Ω cm range were used to calibrate the SR measurement.

The I-V characteristics of Schottky junctions in the Fe-deposited area at room temperature were dominated by the series resistance and leakage. The series resistance on the Fe-deposited area has a high scatter. The Schottky junction prepared on silicon outside the Fe-deposited area has 0.73 V built-in voltage and is appropriate for identification of defects by DLTS. SR measurements were carried out on beveled samples of the Fe-deposited area. It shows that the resistivity in the Fe-deposited region is an order of magnitude higher in about 0.3-0.4 μm depth. The resistivity in the Fe-deposited region has shown large scatter. The silicon in about 1 μm depth below the Fe deposition exhibits resistivity appropriate for the silicon starting wafer.

The C-V characteristics of a Schottky junction prepared on the Fe-deposited area and on the free silicon are shown in Figure 1. The capacitance of the Schottky junction on the Fe-deposited area is larger, indicating that the Fe-generated defect concentration in this area in about 0.5 μm depth is few time 10¹⁶/cm³. This defect concentration is an order of magnitude larger than the 2 × 10¹⁵/cm³ doping determined from the 1/C ²-V plot measured in junctions prepared on the silicon surface. These defects are donor type deep level defects, situated about 250-300 meV below the conduction band edge.

In the Fe-deposited area SCM has shown a patterned surface on the 1 μm scale. The SCM contrast was clear; however, comparison of SCM images with secondary electron microscopy and AFM images shows that the quantum dots cannot be resolved by SCM 7 . A summary of the SCM measurements is shown in Figure 2. dC/dV-bias characteristics at 10 and 90 kHz modulation frequencies are shown in Figure 2a. The bias dependence of dC/dV in the Fe-deposited area is weak as is shown in Figure 2a. Outside the Fe-deposited area the sign of the peak in dC/dV has changed by varying the bias modulation frequency from 10 to 90 kHz as it is shown in Figure 2a. The position of the peak at about 5 V bias was independent of the modulation frequency, however, its amplitude varied with bias modulation frequency as it is shown in Figure 2b. The scans repeated with increasing and decreasing bias modulation frequencies exhibited some hysteresis indicated by Si up and Si down in Figure 2b. The change in the sign of dC/dV can be explained by defects on the surface.

DLTS identified the Fe-related defects in the Fe-deposited area; however, weak junction characteristics prevent proper evaluation of the defects by DLTS. C-V profile has shown that in the Fe-deposited area the deep defect concentration is few times 10¹⁶/cm³, order of magnitude larger than the doping of the starting silicon wafer in about 0.5 μm depth, which does not suit for DLTS measurements.

DLTS spectra measured in a Schottky junction outside the Fe deposition area are shown in Figure 3a. The spectra were recorded at -5 V reverse bias and 0 V bias, 5 μs filling pulses. The spectra are broad, indicating that the defect activation energy is distributed. The depth profile measured by DLTS is shown in Figure 3b. The defects are localized at about 200 nm from the silicon surface. The activation energy of the defect determined by Arrhenius plot shown in Figure 3c agrees with a defect attributed to Fe in silicon 12 . We remark that the depth profile of the defect may be also interpreted as a distributed energy surface state in 5 × 10¹⁰/cm² density, since the depth resolution of the capacitance DLTS technique is not satisfactory to distinguish these details.

A measuring tip was shaped from an 80-μm diameter tungsten wire to an approximately 100 nm radius. It was placed in a shield extending to about 0.5 mm from the surface, to reduce the stray capacitance. The tip was positioned as near as possible without measurable current (few pA) through the tip-wafer junction. It represents an MIS structure. In the Fe-deposited area the tip-wafer capacitance did not depend on the applied bias and no DLTS signal was detected. It is explained by the high defect concentration surface layer.

The measured scanning tip C-V characteristic outside the Fe deposition is shown in Figure 4a. The scanning tip DLTS frequency scan spectrum measured in the same position is shown in Figure 4b. The spectra were measured at room temperature. The spectra measured in different position on the surface show a scatter in amplitude and peak position. This property is analogous to the large scatter observed by SCM outside the Fe deposition area, and the scatter of the DLTS spectra measured in different position Schottky junctions.