Figure 5.

Comparison of layout area between the previous emulator circuit [[4]] and the proposed emulator circuit. The previous emulator circuit has a layout area as large as 1,400 × 1,000 μm2and the proposed emulator can be placed in an area as small as 280 × 160 μm2.

Shin et al. Nanoscale Research Letters 2013 8:454   doi:10.1186/1556-276X-8-454
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