Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design
1 School of Electrical Engineering, Kookmin University, Seoul 136-702, Korea
2 Division of Electronics and Information Engineering, Chonbuk National University, Jeonju 561-756, Korea
Nanoscale Research Letters 2013, 8:454 doi:10.1186/1556-276X-8-454Published: 1 November 2013
In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory.