Figure 4.

Schematic of the simulated chamber, simulated velocity vector graphs, and simulated gas velocity. (a) Schematic of the simulated chamber containing a 14 × 14 SiNW array of diameter 0.2 μm and height 1.0 μm, and at a distance of 0.2 μm between adjacent NWs. (b) Simulated velocity vector graphs in the given areas as the red square indicated in (a). A laminar flow above the NW array and a turbulent flow in the gap between the NWs are obtained. (c) Simulated gas velocity at the mesh points at the y-z-plane along the z-axis. Point A presents the top of NWs. The inset in (c) gives the schematic illustrating the coverage of α-Si:H layers on SiNWs and the built-in electrical field.

Li et al. Nanoscale Research Letters 2013 8:396   doi:10.1186/1556-276X-8-396
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