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Open Access Nano Express

Interface traps and quantum size effects on the retention time in nanoscale memory devices

Ling-Feng Mao

Author affiliations

Institute of Intelligent Structure and System, School of Urban Rail Transportation, Soochow University, Suzhou 215006, China

Citation and License

Nanoscale Research Letters 2013, 8:369  doi:10.1186/1556-276X-8-369

Published: 29 August 2013

Abstract

Based on the analysis of Poisson equation, an analytical surface potential model including interface charge density for nanocrystalline (NC) germanium (Ge) memory devices with p-type silicon substrate has been proposed. Thus, the effects of Pb defects at Si(110)/SiO2, Si(111)/SiO2, and Si(100)/SiO2 interfaces on the retention time have been calculated after quantum size effects have been considered. The results show that the interface trap density has a large effect on the electric field across the tunneling oxide layer and leakage current. This letter demonstrates that the retention time firstly increases with the decrease in diameter of NC Ge and then rapidly decreases with the diameter when it is a few nanometers. This implies that the interface defects, its energy distribution, and the NC size should be seriously considered in the aim to improve the retention time from different technological processes. The experimental data reported in the literature support the theoretical expectation.