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Highly organised and dense vertical silicon nanowire arrays grown in porous alumina template on <100> silicon wafers

Therese Gorisse12*, Ludovic Dupré2, Pascal Gentile2, Mickael Martin1, Marc Zelsmann1 and Denis Buttard23

Author Affiliations

1 CNRS/UJF-Grenoble1/CEA LTM, 17 rue des Martyrs, Grenoble 38054, France

2 SiNaPS Lab - SP2M, UMR-E CEA/UJF-Grenoble 1, INAC, Grenoble 38054, France

3 Université Joseph Fourier/IUT-1, 17 quai C. Bernard, Grenoble 38000, France

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Nanoscale Research Letters 2013, 8:287  doi:10.1186/1556-276X-8-287

Published: 17 June 2013


In this work, nanoimprint lithography combined with standard anodization etching is used to make perfectly organised triangular arrays of vertical cylindrical alumina nanopores onto standard <100>−oriented silicon wafers. Both the pore diameter and the period of alumina porous array are well controlled and can be tuned: the periods vary from 80 to 460 nm, and the diameters vary from 15 nm to any required diameter. These porous thin layers are then successfully used as templates for the guided epitaxial growth of organised mono-crystalline silicon nanowire arrays in a chemical vapour deposition chamber. We report the densities of silicon nanowires up to 9 × 109 cm−2 organised in highly regular arrays with excellent diameter distribution. All process steps are demonstrated on surfaces up to 2 × 2 cm2. Specific emphasis was made to select techniques compatible with microelectronic fabrication standards, adaptable to large surface samples and with a reasonable cost. Achievements made in the quality of the porous alumina array, therefore on the silicon nanowire array, widen the number of potential applications for this technology, such as optical detectors or biological sensors.

Anodic alumina oxide; Nanoimprint lithography; Templates; Chemical vapour deposition; Nanowires; Silicon; Hexagonal array; Defect-free