Figure 4.

Schematic diagram, charge-trapping phenomena, and typical I-V hysteresis and retention characteristics. (a) Schematic diagram of the IrOx/Al2O3/Ge NWs/SiO2/p-Si MOS structure. (b) Charge-trapping phenomena observed by C-V measurements, proving the core-shell Ge/GeOx nanowires to contain defects. (c) Typical I-V hysteresis characteristics of the resistive switching memory device with a MOS structure. A low CC of <20 μA is needed to operate this RRAM device. (d) Retention characteristics of the device.

Prakash et al. Nanoscale Research Letters 2013 8:220   doi:10.1186/1556-276X-8-220
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