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Dislocation reduction of InAs nanofins prepared on Si substrate using metal-organic vapor-phase epitaxy

Chao-Wei Hsu*, Yung-Feng Chen and Yan-Kuin Su*

Author Affiliations

Department of Electrical Engineering & Advanced Optoelectronic Technology Center, Institute of Microelectronics, National Cheng Kung University, 1 University Rd, Tainan City, 701, Taiwan

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Nanoscale Research Letters 2012, 7:642  doi:10.1186/1556-276X-7-642

Published: 23 November 2012


InAs nanofins were prepared on a nanopatterned Si (001) substrate by metal-organic vapor-phase epitaxy. The threading dislocations, stacked on the lowest-energy-facet plane {111}, move along the SiO2 walls, resulting in a dislocation reduction, as confirmed by transmission electron microscopy. The dislocations were trapped within a thin InAs epilayer. The obtained 90-nm-wide InAs nanofins with an almost etching-pit-free surface do not require complex intermediate-layer epitaxial growth processes and large thickness typically required for conventional epitaxial growth.

Threading dislocations; Metal-organic vapor-phase epitaxy; InAs; Nanofins