Open Access Nano Express

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET

Michael Loong Peng Tan12*, Georgios Lentaris2 and Gehan AJ Amaratunga2

Author Affiliations

1 Faculty of Electrical Engineering, Universiti Teknologi Malaysia, UTM Skudai, Johor 81310, Malaysia

2 Electrical Engineering Division, University of Cambridge, 9 J.J. Thomson Ave, Cambridge CB3 0FA, UK

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Nanoscale Research Letters 2012, 7:467  doi:10.1186/1556-276X-7-467

Published: 19 August 2012

Abstract

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency.

Keywords:
Device modeling; HSPICE; Benchmarking; MOSFET; CNTFET; Logic gates