Abstract
The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metaloxidesemiconductor fieldeffect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the draininduced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current onoff ratio (I_{on}/I_{off}), energydelay product, and powerdelay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube fieldeffect transistors (CNTFETs) are compatible with the 45nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency.
Keywords:
Device modeling; HSPICE; Benchmarking; MOSFET; CNTFET; Logic gatesBackground
Carbon nanotubes (CNTs) have been proposed as an alternative channel material to silicon (Si), based on their quantum transport properties which, in principle, allow ballistic transport at room temperature. CNT ballistic modeling [1] has been used to assess the performance of the device at the HSPICE circuit level [2]. Device modeling is vital for projecting the practical performance of a CNT transistor as a switching device in integrated circuits (ICs).
We report the potential of a CNT channel through modeling as a substitute to a silicon channel in a scaled metaloxidesemiconductor fieldeffect transistor (MOSFET) for logic applications. By scaling the Si transistor and the density of states (DOS) of the CNT, we observe good agreement between CNT and ballistic Si MOSFET [3] in the drain current–voltage (IV) output characteristics. Output current is critical in determining the switching speed of a transistor in logic gates. We show that the output performances of CNT and Si channel devices are similar in the 45nm node experimental data. However, the modeling results point to significant reduction in draininduced barrier lowering (DIBL) and related high field effects in the CNT compared to the shortchannel nanoscale Si MOSFET at the same output current. We also assess the effect of channel area restructuring on electric field properties as well as the role of the DOS in determining CNT current. Unlike in the Si MOSFET, it is seen that the performance of a CNT channel is enhanced when the source/drain width is minimized rather than the channel length due to gatetosource/drain parasitic fringe capacitances. MOSFET scaling according to Moore's law is limited by process controllability.
Methods
Carbon nanotube and MOSFET modeling
A layout of a carbon nanotube fieldeffect transistor (CNTFET) is shown in Figure 1. The area of the channel is defined by the width (W) of the source and drain contacts and the length (L) of the nanotube. Details of the ballistic MOSFET modeling can be found in our previous work [3].
Figure 1. Top view of CNTFET device.
The analytical carbon nanotube model comes from the work of Rahman et al. [4,5] where we have extended the universal DOS spectral function into a numerical calculation for CNT conduction subbands. We have modified the DOS subroutine [6] to account for multimode transport [7]. To improve precision and accuracy in the simulation, the parameters in Table 1 for MOSFET and CNTFET which incorporate quasiballistic transport scattering are extracted from CADENCE [8] and Javey et al. [9], respectively. CNTFET analytical models have been validated and agree well with experimental data [9,10] particularly in the saturation region depicted in Figure 2.
Table 1. Source and drain capacitance for multiple substrate insulator thickness
Figure 2. Simulated CNT drain characteristic versus 80nm experimental data. Simulated singlesubband CNT drain characteristic (solid lines) versus 80nm experimental data with highpotassium (K)doped source and drain doping (filled diamond) at V_{G} = 0 to 1.0 V in 0.2V steps. (Adapted from [9]).
If a CNT can achieve the same current as a MOSFET, an identical channel area (A_{MOS} = A_{CNT}) can be maintained by setting the width of the physical space occupied by the CNTFET to be W_{CNT} = A_{MOS} / L_{CNT}. When W = L for the MOSFET, the general channel area can be expressed as A = (kL)^{2}, where k is the scaling factor. As such, a CNT channel with length, 2kL should attain the same current with W = 0.5kL. Thus, if the physical width of the CNT channel is W ≤ 0.5kL, there will not be any area drawback in output current due to the longer L. In fact, the maximum electric field in CNT is halved, giving E_{mCNT} = E_{mSi} / 2, and is significantly reduced as the CNT channel grows longer. For a CNT with L = 60 nm compared to a Si MOSFET with L = 45 nm, the maximum electric field is E_{m} = 0.83 E_{mSi}.
Device modeling
The top view of CNTFET with the source and drain contacts is shown in Figure 1. The filled black rectangle represents the contact enclosure with dimension extracted from a generic 45nm MOSFET process design kit (PDK) where S = 20 nm, C = 60 nm, and W_{C} = L_{C} = 100 nm. Nine capacitances are introduced into the carbonbased macromodel as illustrated in Figure 3. They are the gate oxide capacitance C_{ox}, quantum capacitance C_{Q}, source capacitance C_{s}, drain capacitance C_{d}, substrate capacitance C_{sub}, sourcetobulk capacitance C_{sb}, draintobulk capacitance C_{db}, gatetosource capacitance C_{gs}, and gatetodrain capacitance C_{gd}. The size of the contact is crucial as it ultimately influences C_{sb} and C_{db}. They are given in Table 1 and can be written as
where t_{ins} is the thickness of the insulator, W is the width of the contact, L is the length of the contact, and ε_{ins} is the permittivity of the insulator. The substrate insulator capacitance C_{sub} for CNTFET is given by
where t_{sub} is the substrate oxide thickness and d is the diameter of CNT. The intrinsic gate capacitance C_{G} of CNTFET is a series combination of gate oxide capacitance C_{ox} and quantum capacitance C_{Q}[11]. The C_{ox} of a CNTFET [1214] is shown to be
Figure 3. HSPICE macromodel for CNTFET.
The quantum capacitance is expressed by [1517]
where g_{s} is the spin degeneracy, g_{v} is the valley degeneracy, E_{Gi} is the bandgap energy, and v_{F} is the Fermi velocity. The step function is equal to 1 when x > 0 and 0 when x < 0. The C_{gs} and C_{gd} are given as
where C_{s} and C_{d} are the source and drain capacitance fitting parameters, respectively, [1,2] that are used to fit the experimental data and L_{g} is the length of the gate. The sum of C_{gd} and C_{db} gives the intrinsic capacitance C_{int}.
The square law is no longer valid for IV formulation of shortchannel MOSFET. Tan et al. [3] succinctly show the transformation of the square law that applies for the long channel to the linear law that is applicable for shortchannel MOSFET. On the other hand, IV formulation for the CNTFET model follows the quantum conductance principle that was developed by Rahman et al. [4,5] and Datta [6]. The IV model can be rewritten in terms of drain voltage V_{d}, source voltage V_{s}, and gate voltage V_{G} that is expressed by
where G_{ON} is the ONconductance, V_{sc} is also known as the channel surface potential [11], E_{F} is the Fermi energy, k_{B} is the Boltzmann constant, T is the temperature, and q is the electric charge. The equation is iteratively solved and hence includes the effect of gate voltage.
Model verification
In this section, the potential of CNT circuit design is assessed. Our simulation results in Figure 4 indicate that CNTFET is able to provide drain current performance comparable to a 45nmgate length MOSFET. The model is successful in predicting expected output current levels in a sub100nmchannel CNT transistor experimental data. The DIBL effects and subthreshold swing (SS) are better suppressed in the CNT device, while the Si transistor demonstrates a moderate DIBL and SS due to shortchannel effects as shown in Table 2. Although the CNT has similar ONcurrent, it sustains I_{on}/I_{off} ratio of two orders of magnitude lower than Si MOSFET. The quantum ONconductance limit of a ballistic singlewalled carbon nanotube (SWCNT) and graphene nanoribbon with perfect contact is G_{ON} = 4e^{2}/h and G_{ON} = 2e^{2}/h (twice the fundamental quantum unit of conductance), respectively. Quantum capacitance C_{Q} is directly proportional to the density of states of the semiconductor but inversely proportional to the electrochemical potential energy. When C_{Q} becomes smaller than C_{ox}, a large quantity of the electrochemical potential energy is needed to occupy the states above the Fermi energy. This results in the reduction in overall intrinsic gate capacitance C_{G} and limits the channel charge in a semiconductor and ultimately the IV characteristic of the FET devices. Comparison in Table 2 shows that MOSFET has a higher cutoff frequency due to higher transconductance as compared to CNTFET with lower capacitances.
Figure 4. I  V characteristic of SWCNT model, semiconducting and metallic CNT experimental data.IV characteristic of a 50nm SWCNT model (dotted lines) demonstrated in comparison to L ≈ 50 nm semiconducting CNT experimental data (filled diamond). Metallic CNT experimental data are also shown (filled circle). Inset shows 45nm MOSFET characteristics where the dimension is given in Table 2. Initial V_{G} at the top for CNT and MOSFET is 1 V with 0.1V steps. (Adapted from [10]).
Table 2. Device model specification at V _{GS } = 1 V
First, MOSFET logic circuits are built based on a 45nm generic PDK. The MOSFET designs are then compared with carbonbased circuit models that consist of prototype digital gates implemented in HSPICE circuit simulator. These CNTFETs use 45nm process design rules, namely the minimum contact size. For a fair assessment, both MOSFET and CNTFET are designed to provide similar current strength (≈46 to 50 μA).
An appropriate CNTFET device was fabricated to investigate the contact resistance. SWCNTs were grown in situ using the bimetal catalyst ironmolybdenum (FeMo) [11] on a silicononinsulator substrate with 200 nm of thermally grown SiO_{2}. Metal contacts were patterned by electron beam lithography, and 60 nm of palladium (Pd) contacts was deposited to form a back gate geometry transistor. The spacing between the Pd contacts varied between 56.6 nm and 1.06 μm as shown in Figure 5.
Figure 5. Scanning electron microscope image of Pd contacts over the nanotube with each contact being labeled. Black arrows are used to point to the SWCNT.
A fourprobe measurement was carried out at room temperature to extract the resistance characteristics of the carbon nanotube that was used to form the transistor channel. The normalized resistances were 0.495, 0.744, 0.118, and 0.450 MΩ/nm for R_{2,3}, R_{2,4}, R_{3,4}, and R_{4,5}, respectively, where indices indicate Pd contact labels. The diameter of the SWCNT is 1.5 nm. Calculation shows that the 415nm nanotube resistance is 27.8 kΩ that is almost equal to the theoretical R_{ON} = h/q^{2} = 25.812 kΩ and four times larger than the theoretically lowest quantum resistance of the SWCNT, R_{ON} = h/4q^{2} = 6.5 kΩ.
Though at 415nm channel length ballistic transport is not preserved in the CNT, it is still only factor 4 larger than the theoretically expected minimum, suggesting that scattering is not extensive. Nevertheless, the model which assumes ballistic transport predicts similar saturation current levels (≈50 μA) for both the 50 and 415nm channel devices, as illustrated in Figure 5. Practically, this suggests that one must have CNT channel lengths below approximately 100 nm or even low contact resistance in order to utilize ballistic transport in them.
Results and discussion
Circuit analysis
CNT circuit logic operation is simulated in HSPICE based on the compact models described in the ‘Model verification’ section. Figures 6, 7, 8, 9, and 10 show the schematic of NOT, NAND2, NOR2, NAND3, and NOR3 gates and their corresponding input and output waveform, respectively. It is shown that CNTFETs are able to provide correct logical operation as MOSFET from the output waveform. In this simulation, it is assumed that both the ntype and ptype CNTFETs have symmetrical IV characteristics. The performance evaluation of these Boolean operations is listed in Table 3.
Figure 6. Schematic of NOT gate with parasitic capacitance (a); input and output waveforms for CNTFET (b).
Figure 7. Schematic of twoinput NAND2 gate with parasitic capacitance (a); input and output waveforms for CNTFET (b).
Figure 8. Schematic of twoinput NOR2 gate with parasitic capacitance (a); input and output waveforms for CNTFET (b).
Figure 9. Schematic of threeinput NAND3 gate with parasitic capacitance (a); input and output waveforms for CNTFET (b).
Figure 10. Schematic of threeinput NOR3 gate with parasitic capacitance (a); input and output waveforms for CNTFET (b).
Table 3. 45nm process propagation delay computation between CNTFET (with and without interconnect) and MOSFET (postlayout simulation)
Performance evaluation
The unity current gain cutoff frequency for the CNTFET circuit model is depicted in Figure 11. The model uses a copper interconnect of 45 nm with a 100nm and 500nm substrate insulator thickness. The interconnect length varies from 0.01 to 100 μm. The length of interconnects affects considerably the frequency response. The lower length interconnect enhances the cutoff frequency. The substrate thickness also plays an active role in lower length domain. No distinction with the substrate thickness is visible beyond 1μm interconnect length. The figure of merit for logic devices, namely powerdelay product (PDP) and energydelay product (EDP) metrics, are given as
where P_{av} is the average power and t_{p} is the propagation delay.
Figure 11. Cutoff frequency for CNTFET. Cutoff frequency for CNTFET with interconnect length from 0.01 to 100 μm with a source and drain contact area equivalent to that of a 45nm MOSFET and substrate insulator thickness of 100nm and 500nm.
Figure 12 shows the PDP of CNTFET and MOSFET logic gates for the 45nm process. The simulation results show that the PDP of CNTFETbased gates are lower than that of MOSFETbased gates by several orders of magnitude [18]. For the 45nm process, the PDP of CNTFETbased gates is two times smaller than that of MOSFETbased gates with L_{wire} = 5 μm. It increases to 1,000 times without interconnect (L_{wire} = 0 μm).
Figure 12. PDP of CNTFET versus MOSFET.
Figure 13 shows the EDP of CNTFET and MOSFET logic gates for the 45nm process. EDP for CNTFETbased gates with 5 μm is comparable to MOSFET. As a result, the wire length should be kept shorter than 5 μm in order to obtain energyefficient lowpower architecture.
Figure 13. EDP of CNTFET versus MOSFET.
Figures 14 and 15 show 3D plots of PDP and EDP for CNTFET with copper interconnect up to 5 μm in length. We observe a 28% improvement of PDP while EDP reduces by 39% for NAND3 that adopts the 45nm process compared to the one that uses the 90nm process contact size.
Figure 14. 3D plot of PDP of CNTFET logic gates. The copper interconnect length is up to 5 μm for t_{node} = 45 nm and t_{sub} = 500 nm.
Figure 15. 3D plot of EDP of CNTFET logic gates. The copper interconnect length up to 5 μm for t_{node} = 45 nm and t_{sub} = 500 nm.
Table 3 shows the average propagation delay, t_{p}, for logic gates NOT, NAND2, NAND3, NOR2, and NOR3 for CNTFET with and without interconnect in comparison with MOSFET during postlayout simulation. It is found that NAND3 or NOR3 has the largest propagation delay since both of them has multiple fanin and fanout each. In the digital logic simulation of CNTFET, we use an average length of 5 μm per fanout.
Conclusions
We have established that a longer channel CNT is capable of delivering output currents comparable to those from a 45nmnode Si MOSFET. This is possible due to the preservation of ballistic transport over distances approaching 100 nm and the higher current density of a single CNT forming the channel. Consequently, in the same practical channel area, a CNT allows reduction of shortchannel effects as it has a lower E_{max}, leading to a lower DIBL and off current.
Devices with thicker substrate insulator and smaller source drain contact area give the highest frequency. In addition to that, logic gates NOT, NAND2, NAND3, NOR2, and NOR3 and their corresponding input and output waveforms are given. The interconnect length of cascading logic gates has a profound effect on the signal propagation delay. In the digital logic simulation, the key limiting factor for highspeed CNTbased chips is the interconnect itself. The performance enhancement of these carbonbased material is negligible if the interconnect capacitance is not reduced significantly with transistor feature size. Bundled metallic MWCNTs are seen as a potential candidate to replace copper interconnects as future IC interconnects once the challenges of integrating CNT interconnects onto existing manufacturing processes are met.
We also show that ballistic transport is not maintained in a CNT when contact resistance is large. A good fit to the data output characteristics from a 50nm CNT channel device is obtained. As mean free path in a CNT is very long, often exceeding 1 μm, the ballistic process plays a predominant role, similar to one discussed extensively by Riyadi and Arora [19]. In fact, they define a new feature, named ballisticity. The truly ballistic transport is possible as channel length approaches zero. In a finite length, there are always finite probabilities of scattering.
Competing interests
The authors declare that they have no competing interests.
Authors’ contributions
MLPT designed and carried out the device modeling and simulation work, analyzed the data, and drafted the manuscript. GL carried out the experimental work and fabricated the SWCNT. GAJA supervised the research work and helped amend the manuscript. All authors read and approved the final manuscript.
Authors’ informations
MLPT was born in Bukit Mertajam, Penang, Malaysia, in 1981. He received his B. Eng. (electricaltelecommunication) and M. Eng. (electrical) degrees from Universiti Teknologi Malaysia (UTM), Skudai, Malaysia, in 2003 and 2006, respectively. He conducted his postgraduate research in nanoscale MOSFET modeling at the Intel Penang Design Center, Penang, Malaysia. He recently obtained his Ph.D. degree in 2011 at the University of Cambridge, Cambridge, UK. He is a senior lecturer at UTM. His present research interests are in device modeling and circuit simulation of carbon nanotube, graphene nanoribbon, and MOSFET. MLPT is an IEEE member, member of IET (MIET), graduate member of IEM (GRAD IEM), and member of Queens' College. GL was born in Chania, Crete, Greece in 1983. He holds a B. Eng. (computing and robotic systems) degree from the Department of Electric Engineering in Liverpool University and a Ph.D. degree in engineering from the University of Cambridge. His Ph.D. thesis was in the area of fabricating and characterizing singlewalled carbon nanotubes and ZnO nanowire transistors and sensors. He has also worked as a researcher at Nokia's Eurolab between 2009 and 2011 and particularly in developing novel sensors as part of Nokia's Nanosensing group. He, as part of CambridgeM.I.T iTeams, examines, identifies, and analyzes commercial potentials for an Intelligent Textbook technology, which uses an artificial intelligence engine, with real target customers in relevant industries. At present, GL is interested in pursuing a career that combines technology and analytical expertise, veiled in a business management environment. He is a member of Churchill College. GAJA received his B.Sc. degree in electrical/electronic engineering from Cardiff University, Wales, UK, in 1979 and his Ph.D. degree in electrical/electronic engineering from the University of Cambridge, Cambridge, UK, in 1983. He has held the 1966 Professorship in Engineering with the University of Cambridge since 1998. He currently heads the Electronics, Power and Energy Conversion Group, one of four major research groups within the Electrical Engineering Division of the Cambridge Engineering Faculty. He has worked for 25 years on integrated and discrete electronic devices for power conversion and on the science and technology of carbonbased electronics for 22 years. He has an active research program on the synthesis and electronic applications of carbon nanotubes and other nanoscale materials. He also has research interest in nanomagnetic materials for spin transport devices. He currently sits on the steering committee of the NokiaCambridge University Strategic Collaboration on Nanoscience and Nanotechnology and is the head of the NokiaCU Nanotechnology for Energy Programme. His current research is focused on integrated power conversion circuits. He has previously held faculty positions at the University of Liverpool (Chair in Electrical Engineering), University of Cambridge, and University of Southampton. He has held the UK Royal Academy of Engineering Overseas Research Award at Stanford University, Stanford, CA, USA, and been a Royal Society visitor at the School of Physics, University of Sydney, Sydney, New South Wales, Australia. He has published over 450 journal and conference papers. GAJA was elected a Fellow of the Royal Academy of Engineering in 2004. In 2007, he was awarded the Royal Academy of Engineering Silver Medal ‘for outstanding personal contributions to British engineering.’
Acknowledgments
MLPT thanks the Ministry of Higher Education Malaysia and the Universiti Teknologi Malaysia (UTM) for the award of advanced study fellowship leading to a Ph.D. degree at the University of Cambridge. This work is partially supported by a New Academic Staff (NAS) research grant (vot no.: R.J130000.7723.4P030) and the UTM Research University Grant (GUP) (vot no.: Q.J130000.2623.05J42). The authors also gratefully acknowledge the suggestions made by anonymous reviewers that have enhanced the quality of the manuscript greatly.
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