High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure
1 Department of Electronic Engineering, Minghsin University of Science and Technology, Hsinchu 30401, Taiwan
2 1Dept. of Electronic Engineering, Minghsin University of Science and Technology, Hsinchu, 30401, Taiwan
3 National Nano Device Laboratories, Hsinchu 30078, Taiwan
4 Department of Materials and Resources Engineering, National Taipei University of Technology, Taipei, 10608, Taiwan
5 ADATA Technology Company, New Taipei, 23553, Taiwan
Nanoscale Research Letters 2012, 7:431 doi:10.1186/1556-276X-7-431Published: 1 August 2012
A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal–semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials.