Figure 3.

52° tilted SEM images of different sized NW devices before the gate stack formation. (a) A tiny NW device showing NWs exposed on both sides of the temporary dielectric step, (b) a mid-sized NW device, and (c) a large-sized NW device.

Su et al. Nanoscale Research Letters 2012 7:339   doi:10.1186/1556-276X-7-339
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