Figure 1.

Schematic process flow of the proposed GAA JL NW device. (a) A sandwich stack of nitride/TEOS oxide/nitride layers was sequentially deposited and then patterned on a Si substrate capped with a 200-nm-thick wet oxide. Next, selective lateral etching of the TEOS oxide layer was performed using diluted HF solution to form a sub-100-nm cavity underneath both sides of the top nitride. (b) Deposition of an in situ phosphorus-doped poly-Si layer. (c) The NW doped channels (denoted as DC) and S/D regions were defined simultaneously. (d) After etching off the nitride and oxide surrounding the NW channels, the high-κ/metal gate stack structure was formed using the atomic-layer deposition system to conformally deposit 10-nm Al2O3 and 10-nm TiN films onto the NW channel.

Su et al. Nanoscale Research Letters 2012 7:339   doi:10.1186/1556-276X-7-339
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