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Low-temperature poly-Si nanowire junctionless devices with gate-all-around TiN/Al2O3 stack structure using an implant-free technique

Chun-Jung Su12, Tzu-I Tsai3, Horng-Chih Lin24*, Tiao-Yuan Huang2 and Tien-Sheng Chao3

Author affiliations

1 Nano Facility Center, National Chiao Tung University, Hsinchu, 300, Taiwan

2 Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, 300, Taiwan

3 Department of Electrophysics, National Chiao Tung University, Hsinchu, 300, Taiwan

4 National Nano Device Laboratories, Hsinchu, 300, Taiwan

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Citation and License

Nanoscale Research Letters 2012, 7:339  doi:10.1186/1556-276X-7-339

Published: 22 June 2012


In this work, we present a gate-all-around (GAA) low-temperature poly-Si nanowire (NW) junctionless device with TiN/Al2O3 gate stack using an implant-free approach. Since the source/drain and channel regions are sharing one in situ phosphorous-doped poly-Si material, the process flow and cost could be efficiently reduced. Owing to the GAA configuration and small volume of NW channels, the fabricated devices with heavily doped channels display superior switching behaviors and excellent immunity to short-channel effects. Besides, the negative fixed charges in Al2O3 are found to be helpful to obtain desirable positive threshold voltages for the n+-poly-Si channel devices. Thus, the simple and low-cost fabrication method along with excellent device characteristics makes the proposed GAA NW transistor a promising candidate for future 3-D electronics and system-on-panel applications.

Accumulation mode; Gate-all-around; Junctionless; Low-temperature poly-Si; Nanowire