Figure 8.

Hysteresis behaviors of top-gate NW FET and the switching characteristics. (a) Hysteresis behaviors of a top-gate NW FET as a function of the sweep range of gate voltages. Compared with the hysteretic behavior of a back-gate FET with a clockwise hysteresis loop, devices with the top-gate structure show a counterclockwise hysteresis loop, confirming that the origin of such hysteretic behaviors is due to the polarization of FEs. Arrows indicate gate voltage sweep directions. (b) Switching characteristics of a device with a top gate structure measured with VDS =0.1 V and VG = 0 V, clearly showing that a FeFET functions as a two-bit memory with four different conductance states defined as 00, 01, 10, and 11 after the application of gate voltage pulses of −25, +12, +15, and +25 V, respectively.

Liu et al. Nanoscale Research Letters 2012 7:285   doi:10.1186/1556-276X-7-285
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