Figure 4.

Schematic circuit diagram of In2O3nanowire FeFET (a) and characteristics of PZT-gated In2O3NW transistor (b). The PZT-gated In2O3 NW transistor with VDS = −0.1 V shows pronounced hysteresis. ‘1’ and ‘0’ denote two states at VG = 0 V for the memory operation.

Liu et al. Nanoscale Research Letters 2012 7:285   doi:10.1186/1556-276X-7-285
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