Figure 4.

Two-layer synchronized wire crossing. The left image (L1:X1-Y1) shows the clocking scheme of wire X1-Y1. It is based on a diagonal pipelined transmission with blocks of two cells, producing a total delay of one clock cycle. The middle and right images show the clocking scheme of wire X2-Y2. The middle image (L1:X2-Y2) the part on layer L1; note that the clocking scheme is such that the active cells cause no interference with the cells carrying information of wire X1-Y1. The right image (L2:X2-Y2) shows the part on layer L2, where the same concept of diagonal pipelined transmission is used as for line X1-Y1.

Bajec and Pečar Nanoscale Research Letters 2012 7:221   doi:10.1186/1556-276X-7-221
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