Figure 1.

Illustration of the key process steps for fabricating the JL NW SONOS device. (a) A dielectric stack consisting of top nitride/TEOS/bottom nitride before patterning. (b) Formation of the nano-cavities at the two sides of the stack. (c) Deposition of an n+-doped poly-Si film. (d) Formation of the S/D regions and NW channels by anisotropic dry etching. (e) Final device structure featuring the gate-all-around configuration with an O/N/O gate dielectric stack. (f) Schematic top-view layout of the device.

Su et al. Nanoscale Research Letters 2012 7:162   doi:10.1186/1556-276X-7-162
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