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Open Access Nano Express

Carbon nanotube bumps for the flip chip packaging system

Chin Chong Yap12, Christophe Brun13, Dunlin Tan12, Hong Li2, Edwin Hang Tong Teo124*, Dominique Baillargeat1 and Beng Kang Tay12

Author Affiliations

1 CINTRA CNRS/NTU/THALES, UMI 3288, Research Techno Plaza, 50 Nanyang Drive, Border X Block, Level 6, Singapore, 637553, Singapore

2 School of Electrical and Electronics Engineering, Nanyang Technological University, Block S1, 50 Nanyang Avenue, Singapore, 639798, Singapore

3 XLIM UMR 6172, Université de Limoges/CNRS, 123 Avenue Albert Thomas, Limoges Cedex, 87060, France

4 Temasek Laboratories@NTU, Research Techno Plaza, 50 Nanyang Drive, Border X Block, Level 9, Singapore, 637553, Singapore

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Nanoscale Research Letters 2012, 7:105  doi:10.1186/1556-276X-7-105

Published: 7 February 2012

Abstract

Carbon nanotube [CNT] interconnection bump joining methodology has been successfully demonstrated using flip chip test structures with bump pitches smaller than 150 μm. In this study, plasma-enhanced chemical vapor deposition approach is used to grow the CNT bumps onto the Au metallization lines. The CNT bumps on the die substrate are then 'inserted' into the CNT bumps on the carrier substrate to form the electrical connections (interconnection bumps) between each other. The mechanical strength and the concept of reworkable capabilities of the CNT interconnection bumps are investigated. Preliminary electrical characteristics show a linear relationship between current and voltage, suggesting that ohmic contacts are attained.

Keywords:
CNT bumps; interconnects; flip chip; packaging