Open Access Open Badges Nano Express

Effect of ion implantation energy for the synthesis of Ge nanocrystals in SiN films with HfO2/SiO2 stack tunnel dielectrics for memory application

Bhabani Shankar Sahu1*, Florence Gloux2, Abdelilah Slaoui1, Marzia Carrada1, Dominique Muller1, Jesse Groenen2, Caroline Bonafos2 and Sandrine Lhostis3

Author Affiliations

1 InESS, UDS-CNRS, 23 rue du Loess, 67037 Strasbourg, France

2 Groupe Nanomat, CEMES-CNRS, Université de Toulouse, 29 rue J. Marvig, B.P. 94347, 31055 Toulouse, France

3 ST Microelectronics, 850 rue Jean Monnet, 38926 Crolles, France

For all author emails, please log on.

Nanoscale Research Letters 2011, 6:177  doi:10.1186/1556-276X-6-177

Published: 28 February 2011


Ge nanocrystals (Ge-NCs) embedded in SiN dielectrics with HfO2/SiO2 stack tunnel dielectrics were synthesized by utilizing low-energy (≤5 keV) ion implantation method followed by conventional thermal annealing at 800°C, the key variable being Ge+ ion implantation energy. Two different energies (3 and 5 keV) have been chosen for the evolution of Ge-NCs, which have been found to possess significant changes in structural and chemical properties of the Ge+-implanted dielectric films, and well reflected in the charge storage properties of the Al/SiN/Ge-NC + SiN/HfO2/SiO2/Si metal-insulator-semiconductor (MIS) memory structures. No Ge-NC was detected with a lower implantation energy of 3 keV at a dose of 1.5 × 1016 cm-2, whereas a well-defined 2D-array of nearly spherical and well-separated Ge-NCs within the SiN matrix was observed for the higher-energy-implanted (5 keV) sample for the same implanted dose. The MIS memory structures implanted with 5 keV exhibits better charge storage and retention characteristics compared to the low-energy-implanted sample, indicating that the charge storage is predominantly in Ge-NCs in the memory capacitor. A significant memory window of 3.95 V has been observed under the low operating voltage of ± 6 V with good retention properties, indicating the feasibility of these stack structures for low operating voltage, non-volatile memory devices.