Nano-regime Length Scales Extracted from the First Sharp Diffraction Peak in Non-crystalline SiO2 and Related Materials: Device Applications
1 Department of Physics, North Carolina State University, Raleigh, NC, 27695-8202, USA
2 Department of Physics and Astronomy, Rutgers University, Piscataway, NJ, 08854, USA
Nanoscale Research Letters 2010, 5:550-558 doi:10.1007/s11671-009-9520-6Published: 6 January 2010
This paper distinguishes between two different scales of medium range order, MRO, in non-crystalline SiO2: (1) the first is ~0.4 to 0.5 nm and is obtained from the position of the first sharp diffraction peak, FSDP, in the X-ray diffraction structure factor, S(Q), and (2) the second is ~1 nm and is calculated from the FSDP full-width-at-half-maximum FWHM. Many-electron calculations yield Si–O third- and O–O fourth-nearest-neighbor bonding distances in the same 0.4–0.5 nm MRO regime. These derive from the availability of empty Si dπ orbitals for back-donation from occupied O pπ orbitals yielding narrow symmetry determined distributions of third neighbor Si–O, and fourth neighbor O–O distances. These are segments of six member rings contributing to connected six-member rings with ~1 nm length scale within the MRO regime. The unique properties of non-crystalline SiO2 are explained by the encapsulation of six-member ring clusters by five- and seven-member rings on average in a compliant hard-soft nano-scaled inhomogeneous network. This network structure minimizes macroscopic strain, reducing intrinsic bonding defects as well as defect precursors. This inhomogeneous CRN is enabling for applications including thermally grown ~1.5 nm SiO2 layers for Si field effect transistor devices to optical components with centimeter dimensions. There are qualitatively similar length scales in nano-crystalline HfO2 and phase separated Hf silicates based on the primitive unit cell, rather than a ring structure. Hf oxide dielectrics have recently been used as replacement dielectrics for a new generation of Si and Si/Ge devices heralding a transition into nano-scale circuits and systems on a Si chip.