The Characteristics of Seebeck Coefficient in Silicon Nanowires Manufactured by CMOS Compatible Process
1 Electronics and Telecommunications Research Institute (ETRI), Taejon, 305-700, Korea
2 Korea Advanced Institute of Science and Technology (KAIST), Taejon, 305-701, Korea
Nanoscale Research Letters 2010, 5:1654-1657 doi:10.1007/s11671-010-9690-2Published: 18 July 2010
Silicon nanowires are patterned down to 30 nm using complementary metal-oxide-semiconductor (CMOS) compatible process. The electrical conductivities of n-/p-leg nanowires are extracted with the variation of width. Using this structure, Seebeck coefficients are measured. The obtained maximum Seebeck coefficient values are 122 μV/K for p-leg and −94 μV/K for n-leg. The maximum attainable power factor is 0.74 mW/m K2 at room temperature.