Figure 9.

aSchematic illustration of a Zn3P2nanowire based MS-FET.bISDVSDcharacteristics of ap-type Zn3P2nanowire based MS-FET measured at room temperature under gate biases ranging from −0.5 to 0 V with a step of 0.1 V

Shen and Chen Nanoscale Research Letters 2009 4:779-788   doi:10.1007/s11671-009-9338-2