Figure 5.
Configurations of DRAM in different logic states
Xiao et al. Nanoscale Research Letters 2008 3:416 doi:10.1007/s11671-008-9167-8 |
Figure 5.
Configurations of DRAM in different logic states
Xiao et al. Nanoscale Research Letters 2008 3:416 doi:10.1007/s11671-008-9167-8 |
